/*!
    \file    change log.txt
    \brief   change log for GD32H75E firmware

    \version 2026-02-04, V1.3.0, firmware for GD32H75E
*/

/*
    Copyright (c) 2026, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this 
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, 
       this list of conditions and the following disclaimer in the documentation 
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors 
       may be used to endorse or promote products derived from this software without 
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.
*/

******************* V1.3.0 2026-02-04 ******************************************************************************************
______________________Common_________________________________________________________________________________________________
Fix file:
../

fix reason: Add support. 

V1.2.0:

V1.3.0:
Add support for Eembedded builder. 
Adapted to the GD32H75EY-EVAL-V1.0 board.
_____________________________________________________________________________________________________________________________
______________________Common_________________________________________________________________________________________________
Fix file:
../

fix reason: Add support. 

V1.2.0:

V1.3.0:
Add support for MISRA 14.7.
_____________________________________________________________________________________________________________________________
______________________Common_________________________________________________________________________________________________
Fix file:
../Utilities/gd32h75ey_eval.c

fix reason: Format adjustment. 

V1.2.0:

V1.3.0:
Change the printf function to the eval.c file.
_____________________________________________________________________________________________________________________________
______________________Common_________________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32H75E/Include/gd32h75e.h

fix reason: Bug Fix. 

V1.2.0:
1. HAU_TRNG_IRQn

V1.3.0:
1. TRNG_IRQn
2. Delete SDIO0_IRQn, ENET0_IRQn, ENET0_WKUP_IRQn, DCI_IRQn, CAU_IRQn, SAI0_IRQn, TLI_IRQn, TLI_ER_IRQn, IPA_IRQn, SAI1_IRQn, 
RSPDIF_IRQn, SAI2_IRQn, MDIO_IRQn, SDIO1_IRQn, HWSEM_IRQn, RTDEC0_IRQn, RTDEC1_IRQn, ENET1_IRQn, ENET1_WKUP_IRQn.
_____________________________________________________________________________________________________________________________
______________________Common_________________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32H75E/Source/ARM/startup_gd32h75e.s
../Firmware/CMSIS/GD/GD32H75E/Source/IAR/startup_gd32h75e.s

fix reason: Bug Fix. 

V1.2.0:
Delete Function.

V1.3.0:
Delete RTDEC0/RTDEC0 interrupt handler.
____________________________________________________________________________________________________________________________
______________________RCU____________________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32H75E/Source/system_gd32h75e.c

fix reason: Bug Fix. According to the datasheet limitations, update the PLLIN input clock range to 1-2MHz；when RCU_CTL_IRC64MEN
is set to '1',RCU_ADDCTL1_IRC64MDIV cannot be written

V1.2.0:

V1.3.0:
Delete 
    /* configure IRC64M div */
    RCU_ADDCTL1 &= ~(RCU_ADDCTL1_IRC64MDIV);
    RCU_ADDCTL1 |= RCU_IRC64M_DIV1;

in function system_clock_64m_irc64m() and system_clock_480m_irc64m().
_____________________________________________________________________________________________________________________________
______________________EFUSE____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_efuse.c

fix reason: Bug Fix. 

V1.2.0:
void efuse_interrupt_enable(uint32_t interrupt)
{
#ifdef FW_DEBUG_ERR_REPORT
    /* check parameter */
    if(NOT_EFUSE_INT(interrupt)) {
        fw_debug_report_err(EFUSE_MODULE_ID, API_ID(0x000FU), ERR_PARAM_INVALID);
    } else
#endif
    {
        EFUSE_CTL = (uint32_t)interrupt;
    }
}

V1.3.0:
void efuse_interrupt_enable(uint32_t interrupt)
{
#ifdef FW_DEBUG_ERR_REPORT
    /* check parameter */
    if(NOT_EFUSE_INT(interrupt)) {
        fw_debug_report_err(EFUSE_MODULE_ID, API_ID(0x000FU), ERR_PARAM_INVALID);
    } else
#endif
    {
        EFUSE_CTL |= (uint32_t)interrupt;
    }
}
_____________________________________________________________________________________________________________________________
______________________USBHS__________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_syscfg.c

fix reason: Bug Fix. Modify the endpoint number of the register.

V1.2.0:
#define EP7_OUT                                 ((uint8_t)0x06U)        /*!< endpoint out 7 */
#define EP7_IN                                  ((uint8_t)0x86U)        /*!< endpoint in 7 */

V1.3.0:
#define EP7_OUT                                 ((uint8_t)0x07U)        /*!< endpoint out 7 */
#define EP7_IN                                  ((uint8_t)0x87U)        /*!< endpoint in 7 */
_____________________________________________________________________________________________________________________________
______________________SYSCFG_________________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32H75E/Source/system_gd32h75e.c

fix reason: Bug Fix. 

V1.2.0:
uint32_t syscfg_cpu_cache_status_get(uint32_t cache, uint32_t status)
{
......
        /* get DCACHE information */
        case DCACHE_STATUS:
            if(CPU_CACHE_ERROR_DETECTION == status) {
                /* return detection information */
                value = (uint32_t)((SYSCFG_CPUDCAC & SYSCFG_CPUICAC_CPU_ICDET) >> 28U);
            } else {
                /* return error bank information */
                value = (uint32_t)((SYSCFG_CPUDCAC & SYSCFG_CPUICAC_CPU_ICERR) >> 6U);
            }
......
}
V1.3.0:
uint32_t syscfg_cpu_cache_status_get(uint32_t cache, uint32_t status)
{
......
        /* get DCACHE information */
        case DCACHE_STATUS:
            if(CPU_CACHE_ERROR_DETECTION == status) {
                /* return detection information */
                value = (uint32_t)((SYSCFG_CPUDCAC & SYSCFG_CPUDCAC_CPU_DCDET) >> 28U);
            } else {
                /* return error bank information */
                value = (uint32_t)((SYSCFG_CPUDCAC & SYSCFG_CPUDCAC_CPU_DCERR) >> 6U);
            }
......
}
______________________PMU____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_pmu.h

fix reason: Bug Fix. 

V1.2.0:
#define PMU_CTL2_VCRSEL                 BIT(8)                              /*!< VBAT battery charging resistor selection */
#define PMU_CTL2_VCEN                   BIT(9)                              /*!< VBAT battery charging enable */

V1.3.0:
#define PMU_CTL2_VCEN                   BIT(8)                              /*!< VBAT battery charging enable */
#define PMU_CTL2_VCRSEL                 BIT(9)                              /*!< VBAT battery charging resistor selection */
_____________________________________________________________________________________________________________________________
______________________SPI____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_spi.h
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_spi.c

fix reason: Delete function. 

V1.2.0:

V1.3.0:
Delete macro SPI_QCTL_IO23_DRV.
Delete function spi_quad_io23_output_enable and spi_quad_io23_output_disable.
_____________________________________________________________________________________________________________________________
______________________MISC____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_misc.h
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_misc.c

fix reason: Add function. 

V1.2.0:

V1.3.0:
Add function nvic_system_reset().
_____________________________________________________________________________________________________________________________
______________________MISC____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_misc.c

fix reason: Bug fix. 

V1.2.0:
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority,
                     uint8_t nvic_irq_sub_priority)
{
#ifdef FW_DEBUG_ERR_REPORT
    if(NOT_NVIC_IRQ_PRIORITY(nvic_irq_pre_priority)) {
        fw_debug_report_err(MISC_MODULE_ID, API_ID(0x0002U), ERR_PARAM_OUT_OF_RANGE);
    } else if(NOT_NVIC_IRQ_PRIORITY(nvic_irq_sub_priority)) {
        fw_debug_report_err(MISC_MODULE_ID, API_ID(0x0002U), ERR_PARAM_OUT_OF_RANGE);
    } else
#endif /* FW_DEBUG_ERR_REPORT */
    {
        uint32_t temp_priority, temp_pre, temp_sub;
        /* use the priority group value to get the temp_pre and the temp_sub */
        if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE0_SUB4) {
            temp_pre = 0U;
            temp_sub = 0x4U;
        } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE1_SUB3) {
            temp_pre = 1U;
            temp_sub = 0x3U;
        } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE2_SUB2) {
            temp_pre = 2U;
            temp_sub = 0x2U;
        } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE3_SUB1) {
            temp_pre = 3U;
            temp_sub = 0x1U;
        } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE4_SUB0) {
            temp_pre = 4U;
            temp_sub = 0x0U;
        } else {
            nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
            temp_pre = 2U;
            temp_sub = 0x2U;
        }
        /* get the temp_priority to fill the NVIC->IP register */
        temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
        temp_priority |= (uint32_t)nvic_irq_sub_priority & ((uint32_t)0x0FU >> (0x4U - temp_sub));
        __NVIC_SetPriority((IRQn_Type)nvic_irq, temp_priority);
        /* enable the selected IRQ */
        NVIC->ISER[(uint8_t)nvic_irq >> 0x05U] = (uint32_t)0x01U << ((uint8_t)nvic_irq & (uint8_t)0x1FU);
    }
}

V1.3.0:
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority, \
                     uint8_t nvic_irq_sub_priority)
{
#ifdef FW_DEBUG_ERR_REPORT
    if(NOT_NVIC_IRQ_PRIORITY(nvic_irq_pre_priority)) {
        fw_debug_report_err(MISC_MODULE_ID, API_ID(0x0002U), ERR_PARAM_OUT_OF_RANGE);
    } else if(NOT_NVIC_IRQ_PRIORITY(nvic_irq_sub_priority)) {
        fw_debug_report_err(MISC_MODULE_ID, API_ID(0x0002U), ERR_PARAM_OUT_OF_RANGE);
    } else
#endif /* FW_DEBUG_ERR_REPORT */
    {
        uint32_t nvic_prigroup, nvic_priority;

        /* check current priority group */
        switch(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) {
        case NVIC_PRIGROUP_PRE0_SUB4:
        case NVIC_PRIGROUP_PRE1_SUB3:
        case NVIC_PRIGROUP_PRE2_SUB2:
        case NVIC_PRIGROUP_PRE3_SUB1:
        case NVIC_PRIGROUP_PRE4_SUB0:
            break;
        default:
            nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
            break;
        }

        /* get the priority group value */
        nvic_prigroup = NVIC_GetPriorityGrouping();

        /* encoding the pre-emption priority, subpriority */
        nvic_priority = NVIC_EncodePriority(nvic_prigroup, (uint32_t)nvic_irq_pre_priority, (uint32_t)nvic_irq_sub_priority);

        /* set priority */
        NVIC_SetPriority(nvic_irq, nvic_priority);

        /* enable the selected IRQ */
        NVIC_EnableIRQ(nvic_irq);
    }
}
_____________________________________________________________________________________________________________________________
______________________USART____________________________________________________________________________________________________
Fix file:
../Examples/USART/DMA_transmitter&receiver/main.c

fix reason: Bug Fix. 

V1.2.0:
int main(void)
{
    ......
        /* configure DMA mode */
        dma_circulation_disable(DMA0, DMA_CH1);
        /* enable DMA channel 1 */
        dma_channel_enable(DMA0, DMA_CH1);
        /* USART DMA enable for reception */
        usart_dma_receive_config(USART0, USART_RECEIVE_DMA_ENABLE);

        /* wait DMA channel 1 transfer complete */
        while(RESET == dma_flag_get(DMA0, DMA_CH1, DMA_FLAG_FTF));

        /* invalidate d-cache by address */
        SCB_InvalidateDCache_by_Addr((uint32_t*)rxbuffer, 32);
        printf("\n\r%s\n\r", rxbuffer);
}

V1.3.0:
int main(void)
{
    ......
        /* configure DMA mode */
        dma_circulation_disable(DMA0, DMA_CH1);
        /* enable DMA channel 1 */
        dma_channel_enable(DMA0, DMA_CH1);
        /* USART receive enable */
        usart_receive_config(USART0, USART_RECEIVE_ENABLE);
        /* USART DMA enable for reception */
        usart_dma_receive_config(USART0, USART_RECEIVE_DMA_ENABLE);

        /* wait DMA channel 1 transfer complete */
        while(RESET == dma_flag_get(DMA0, DMA_CH1, DMA_FLAG_FTF));

        /* USART receive disable */
        usart_receive_config(USART0, USART_RECEIVE_DISABLE);

        /* invalidate d-cache by address */
        SCB_InvalidateDCache_by_Addr((uint32_t*)rxbuffer, 32);
        printf("\n\r%s\n\r", rxbuffer);
}
_____________________________________________________________________________________________________________________________
______________________MDMA____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_mdma.h
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_mdma.c

fix reason: Add Function. 

V1.2.0:

V1.3.0:
Add macro MDMA_SECURE_MODE_DISABLE and MDMA_SECURE_MODE_ENABLE.
Add function dma_secure_mode_config.
_____________________________________________________________________________________________________________________________
______________________EXMC____________________________________________________________________________________________________
Fix file:
../Examples/EXMC/SDRAM_swap
../Examples/EXMC/SDRAM
../Examples/EXMC/NORFLASH
../Examples/EXMC/SRAM

fix reason: Delete Function. EXMC_A10 are missing, keeping the SDRAM example is of little significance, so it has been deleted.

V1.2.0:

V1.3.0:
Delete example SDRAM_swap / SDRAM / NORFLASH / SRAM.
_____________________________________________________________________________________________________________________________
______________________CMP____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_cmp.h
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_cmp.c

fix reason: Delete Function. Delete AFSE PG2/PG3/PG4/PK1/PK2 related function.

V1.2.0:

V1.3.0:
Delete the bits as follows and the corresponding functional macros.
 function select for CMPx_OUT */
#define CMP_SR_AFSE_PG3                          BIT(6)                         /*!< PG3 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PG4                          BIT(7)                         /*!< PG4 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PK0                          BIT(8)                         /*!< PK0 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PK1                          BIT(9)                         /*!< PK1 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PK2                          BIT(10)                        /*!< PK2 alternate function select for CMPx_OUT */
_____________________________________________________________________________________________________________________________
______________________EXMC____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_exmc.h
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_exmc.c

fix reason: Add function. 

V1.2.0:

V1.3.0:
Add macro EXMC_NOR_DATABUS_WIDTH_32B.
_____________________________________________________________________________________________________________________________
______________________LPDTS____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_lpdts.h
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_lpdts.c

fix reason: Bug fix. 

V1.2.0:
#define LPDTS_T0_TMP_VAL           ((uint32_t)25U)

int32_t lpdts_temperature_get(void)
{
    uint32_t freq;
    uint32_t count;
    uint32_t t0;
    uint32_t t0_freq;
    uint32_t ramp_coeff;
    uint32_t reg_cfg;
    int32_t temperature;

    /* get the total number of samples */
    count = (LPDTS_DATA & LPDTS_DATA_COVAL);
    /* get LPDTS_CFG configuration */
    reg_cfg = LPDTS_CFG;

    /* get the module frequency on Hz */
    if((reg_cfg & LPDTS_CFG_REFSEL) == LPDTS_CFG_REFSEL) {
        freq = (LXTAL_VALUE * count) / (2U * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET));
    } else {
        freq = (2U * rcu_clock_freq_get(CK_APB1) / count) * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET);
    }

    /* read factory settings */
    t0 = (LPDTS_SDATA & LPDTS_SDATA_VAL) >> LPDTS_SDATA_VAL_OFFSET;
    if(t0 == 0U) {
        t0 = LPDTS_T0_TMP_VAL;
    }

    /* get the T0 frequency on Hz */
    t0_freq = (LPDTS_SDATA & LPDTS_SDATA_FREQ) * 100U;
    /* get the ramp coefficient for the temperature sensor on deg C/Hz */
    ramp_coeff = LPDTS_RDATA & LPDTS_RDATA_RCVAL;

    /* figure out the temperature deg C */
    temperature = (int32_t)t0 + (((int32_t)freq - (int32_t)t0_freq) / (int32_t)ramp_coeff);

    return temperature;
}

V1.3.0:
#define LPDTS_T0_TMP_VAL0          (25)
#define LPDTS_T0_TMP_VAL1          (-40)

int32_t lpdts_temperature_get(void)
{
    uint32_t freq;
    uint32_t count;
    int32_t t0;
    uint32_t val;
    uint32_t t0_freq;
    uint32_t ramp_coeff;
    uint32_t reg_cfg;
    int32_t temperature;

    /* get the total number of samples */
    count = (LPDTS_DATA & LPDTS_DATA_COVAL);
    /* get LPDTS_CFG configuration */
    reg_cfg = LPDTS_CFG;

    /* get the module frequency on Hz */
    if((reg_cfg & LPDTS_CFG_REFSEL) == LPDTS_CFG_REFSEL) {
        freq = (LXTAL_VALUE * count) / (2U * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET));
    } else {
        freq = (2U * rcu_clock_freq_get(CK_APB1) / count) * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET);
    }

    /* read factory settings */
    val = (LPDTS_SDATA & LPDTS_SDATA_VAL) >> LPDTS_SDATA_VAL_OFFSET;
    if(val == 0U) {
        t0 = LPDTS_T0_TMP_VAL0;
    } else if(val == 1U) {
        t0 = LPDTS_T0_TMP_VAL1;
    }

    /* get the T0 frequency on Hz */
    t0_freq = (LPDTS_SDATA & LPDTS_SDATA_FREQ) * 100U;
    /* get the ramp coefficient for the temperature sensor on deg C/Hz */
    ramp_coeff = LPDTS_RDATA & LPDTS_RDATA_RCVAL;

    /* figure out the temperature deg C */
    temperature = t0 + (((int32_t)freq - (int32_t)t0_freq) / (int32_t)ramp_coeff);

    return temperature;
}
_____________________________________________________________________________________________________________________________
______________________RTC____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_rtc.h

fix reason: Bug Fix. 

V1.2.0:
#define RTC_ALARM_OUTPUT_PP                RTC_CTL_ALRMOUTTYPE                         /*!< RTC alarm output push-pull mode */

V1.3.0:
#define RTC_ALARM_OUTPUT_PP                RTC_CFG_ALRMOUTTYPE                         /*!< RTC alarm output push-pull mode */
_____________________________________________________________________________________________________________________________
______________________TRIGSEL_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_trigsel.h
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_trigsel.c
../Examples/TRIGSEL/timer0_pwm_trigger_adc/main.c

fix reason: Bug Fix. 

V1.2.0:
    TRIGSEL_OUTPUT_ADC0_REGTRG            = ((uint8_t)0x10U),               /*!< output target peripheral ADC0_REGTRG */
    TRIGSEL_OUTPUT_ADC0_INSTRG            = ((uint8_t)0x11U),               /*!< output target peripheral ADC0_INSTRG */
    TRIGSEL_OUTPUT_ADC1_REGTRG            = ((uint8_t)0x14U),               /*!< output target peripheral ADC1_REGTRG */
    TRIGSEL_OUTPUT_ADC1_INSTRG            = ((uint8_t)0x15U),               /*!< output target peripheral ADC1_INSTRG */
    TRIGSEL_OUTPUT_ADC2_REGTRG            = ((uint8_t)0x18U),               /*!< output target peripheral ADC2_REGTRG */

V1.3.0:
    TRIGSEL_OUTPUT_ADC0_ROUTRG            = ((uint8_t)0x10U),               /*!< output target peripheral ADC0_ROUTRG */
    TRIGSEL_OUTPUT_ADC0_INSTRG            = ((uint8_t)0x11U),               /*!< output target peripheral ADC0_INSTRG */
    TRIGSEL_OUTPUT_ADC1_ROUTRG            = ((uint8_t)0x14U),               /*!< output target peripheral ADC1_ROUTRG */
    TRIGSEL_OUTPUT_ADC1_INSTRG            = ((uint8_t)0x15U),               /*!< output target peripheral ADC1_INSTRG */
    TRIGSEL_OUTPUT_ADC2_ROUTRG            = ((uint8_t)0x18U),               /*!< output target peripheral ADC2_ROUTRG */
_____________________________________________________________________________________________________________________________
______________________FMC____________________________________________________________________________________________________
Fix file:
../Examples/FMC/Erase_Program/main.c
../Examples/FMC/Write_protection/main.c

fix reason: Bug Fix. 

V1.2.0:

V1.3.0:
Add function fmc_all_flags_clear before program/erase flash and option bytes.
_____________________________________________________________________________________________________________________________
______________________USBHS/USBD____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_usbhs_library/driver/Source/drv_usbd_int.c
../Firmware/GD32H75E_usbhs_library/driver/Source/drv_usbh_int.c

fix reason: Bug Fix. 

V1.2.0:
1.
static uint32_t usbd_int_epout(usb_core_driver *udev)
{
......
                if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
                    __IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN;

                    udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - \
                                                                (eplen & DEPLEN_TLEN);
                }
......               
}

2.
static uint32_t usbh_int_pipe_in(usb_core_driver *udev, uint32_t pp_num)
{
......
        case USB_EPTYPE_BULK:
            usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_XF);
......            
}

V1.3.0:
1.
static uint32_t usbd_int_epout(usb_core_driver *udev)
{
......
                if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) {
                    usb_transc *transc = &udev->dev.transc_out[ep_num];
                    __IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN;
                    uint32_t set_len = ((transc->xfer_len + transc->max_len - 1U) / transc->max_len) * transc->max_len;

                    udev->dev.transc_out[ep_num].xfer_count = set_len - (eplen & DEPLEN_TLEN);
                }
......               
}

2.
static uint32_t usbh_int_pipe_in(usb_core_driver *udev, uint32_t pp_num)
{
......
        case USB_EPTYPE_BULK:
            if(USB_USE_DMA == udev->bp.transfer_mode) {
                udev->regs.pr[pp_num]->HCHINTEN |= HCHINTEN_CHIE;
            } else {
                usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_XF);
            }
......            
}
_____________________________________________________________________________________________________________________________
______________________EDOUT____________________________________________________________________________________________________
Fix file:
../Examples/EDOUT/Timer_trigger_edout/gd32h75e_it.h
../Examples/EDOUT/Timer_trigger_edout/gd32h75e_it.c
../Examples/EXTI/Key_external_interrupt_mode/gd32h75e_it.h
../Examples/EXTI/Key_external_interrupt_mode/gd32h75e_it.c

fix reason: Delete function. 

V1.2.0:

V1.3.0:
Delete FPU_IRQHandler function.
_____________________________________________________________________________________________________________________________
______________________ESC____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_esc_library/Include/gd32h75e_esc_ospi.h

fix reason: Delete function. 

V1.2.0:

V1.3.0:
Delete 
/* 64bit value union */
typedef union {
    uint64_t Val;
    uint8_t v[8];
    uint16_t w[4];
    uint32_t z[2];
    struct {
        uint8_t LB;
        uint8_t HB;
        uint8_t UB;
        uint8_t MB;
        uint8_t LLB;
        uint8_t HHB;
        uint8_t UUB;
        uint8_t MMB;
    } byte;
} UINT64_VAL;
_____________________________________________________________________________________________________________________________
______________________USBHS____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_usbhs_library/host/class/msc/Source/usbh_msc_core.c

fix reason: Delete function. 

V1.2.0:
usbh_status usbh_msc_read(usbh_host *uhost, \
                          uint8_t lun, \
                          uint32_t address, \
                          uint8_t *pbuf, \
                          uint32_t length)
{
......
    while(USBH_BUSY == usbh_msc_rdwr_process(uhost, lun)) {
        if(((uhost->control.timer - timeout) > (1000U * length)) || (0U == udev->host.connect_status)) {
            msc->state = MSC_IDLE;
            return USBH_FAIL;
        }
    }
......
}

V1.3.0:
usbh_status usbh_msc_read(usbh_host *uhost, \
                          uint8_t lun, \
                          uint32_t address, \
                          uint8_t *pbuf, \
                          uint32_t length)
{
......
    while(USBH_BUSY == usbh_msc_rdwr_process(uhost, lun)) {
        if(((uhost->control.timer - timeout) > (10000U * length)) || (0U == udev->host.connect_status)) {
            msc->state = MSC_IDLE;
            return USBH_FAIL;
        }
    }
......
}
_____________________________________________________________________________________________________________________________
______________________RCU____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_hpdf.h

fix reason: Bug Fix. 

V1.2.0:
/* HPDF_FLTYEMMAX */
#define HPDF_FLTYEMMAX_MAXDC            BIT(0,2)                        /*!< extremes monitor maximum data channel */
#define HPDF_FLTYEMMAX_MAXVAL           BITS(8,31)                      /*!< extremes monitor maximum value */

/* HPDF_FLTYEMMIN */
#define HPDF_FLTYEMMIN_MINDC            BIT(0,2)                        /*!< extremes monitor minimum data channel */
#define HPDF_FLTYEMMIN_MINVAL           BITS(8,31)                      /*!< extremes monitor minimum value */

/* HPDF_FLTYCT */
#define HPDF_FLTYCT_CTCNT               BIT(4,31)                       /*!< conversion time measured by HPDFCLK */

V1.3.0:
/* HPDF_FLTYEMMAX */
#define HPDF_FLTYEMMAX_MAXDC            BITS(0,2)                       /*!< extremes monitor maximum data channel */
#define HPDF_FLTYEMMAX_MAXVAL           BITS(8,31)                      /*!< extremes monitor maximum value */

/* HPDF_FLTYEMMIN */
#define HPDF_FLTYEMMIN_MINDC            BITS(0,2)                       /*!< extremes monitor minimum data channel */
#define HPDF_FLTYEMMIN_MINVAL           BITS(8,31)                      /*!< extremes monitor minimum value */

/* HPDF_FLTYCT */
#define HPDF_FLTYCT_CTCNT               BITS(4,31)                      /*!< conversion time measured by HPDFCLK */
_____________________________________________________________________________________________________________________________
______________________TMU____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_tmu.h
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_tmu.c

fix reason: Add function. 

V1.2.0:

V1.3.0:
add
/* TMU flag */
#define TMU_FLAG_END                TMU_CS_ENDF                 /*!< end of TMU operation flag */
/* get TMU flag */
FlagStatus tmu_flag_get(uint32_t flag);
_____________________________________________________________________________________________________________________________
______________________TMU____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_tmu.c

fix reason: Support Eembedded builder. 

V1.2.0:
void tmu_two_q31_read(uint32_t* p1, uint32_t* p2)
{
#ifdef FW_DEBUG_ERR_REPORT
    /* check parameter */
    if(NOT_VALID_POINTER(p1)) {
        fw_debug_report_err(TMU_MODULE_ID, API_ID(0x000EU), ERR_PARAM_POINTER);
    } else if(NOT_VALID_POINTER(p2)) {
        fw_debug_report_err(TMU_MODULE_ID, API_ID(0x000EU), ERR_PARAM_POINTER);
    } else
#endif /* FW_DEBUG_ERR_REPORT */
    {
        *p1 = TMU_ODATA;
        *p2 = TMU_ODATA;
    }
}

V1.3.0:
void tmu_two_q31_read(uint32_t* p1, uint32_t* p2)
{
#ifdef FW_DEBUG_ERR_REPORT
    /* check parameter */
    if(NOT_VALID_POINTER(p1)) {
        fw_debug_report_err(TMU_MODULE_ID, API_ID(0x000EU), ERR_PARAM_POINTER);
    } else if(NOT_VALID_POINTER(p2)) {
        fw_debug_report_err(TMU_MODULE_ID, API_ID(0x000EU), ERR_PARAM_POINTER);
    } else
#endif /* FW_DEBUG_ERR_REPORT */
    {
        *p1 = TMU_ODATA;
        __DSB();
        *p2 = TMU_ODATA;
    }
}
_____________________________________________________________________________________________________________________________
______________________RCU____________________________________________________________________________________________________
Fix file:
../Examples/HPDF/sample_internal_parallel_data&inserted_conversion/main.c
../Examples/HPDF/sample_internal_parallel_data&regular_conversion/main.c
../Examples/HPDF/serial_SPI_interface&regular_conversion/main.c

fix reason: Bug Fix. Add DCACHE clear operation before data conversion and invalidate DCACHE after conversion.

V1.2.0:

V1.3.0:
add
//before conversion
    /* clean D-Cache to flush internal_data to memory before HPDF reads it */
    SCB_CleanDCache_by_Addr((uint32_t *)internal_data, sizeof(internal_data));
    __DSB();
    __ISB();
//after conversion
    /* invalidate D-Cache to ensure reading latest data from memory */
    SCB_InvalidateDCache_by_Addr((uint32_t *)conversion_data, sizeof(conversion_data));
    __DSB();
    __ISB();
_____________________________________________________________________________________________________________________________
______________________CAN____________________________________________________________________________________________________
Fix file:
../Examples/CAN/communication_FDmode/main.c
../Examples/CAN/communication_classical_CAN/main.c
../Examples/CAN/communication_FDmode/gd32h75e_it.c
../Examples/CAN/communication_classical_CAN/gd32h75e_it.c

fix reason: Bug Fix. 

V1.2.0:
1.
void communication_check(void)
{
    uint8_t i = 0U;

    /* CAN1 receive data correctly, the received data is printed */
    if(SET == can1_receive_flag) {
        can1_receive_flag = RESET;

        /* check the receive message */
        can_mailbox_receive_data_read(CAN1, 0U, &receive_message);
        if(0U == memcmp(receive_message.data, transmit_message.data, receive_message.data_bytes)) {
            printf("\r\nCAN1 receive data: \r\n");
            for(i = 0U; i < receive_message.data_bytes; i++) {
                printf("%02x ", receive_message.data[i]);
            }
            gd_eval_led_toggle(LED3);
        }
    }
}

2.
void CAN1_Message_IRQHandler(void)
{
    if(RESET != can_interrupt_flag_get(CAN1, CAN_INT_FLAG_MB0)) {
        can_interrupt_flag_clear(CAN1, CAN_INT_FLAG_MB0);
        can1_receive_flag = SET;
    }
}

V1.3.0:
1.
void communication_check(void)
{
    uint8_t i = 0U;

    /* CAN1 receive data correctly, the received data is printed */
    if(SET == can1_receive_flag) {
        can1_receive_flag = RESET;
        if(0U == memcmp(receive_message.data, transmit_message.data, receive_message.data_bytes)) {
            printf("\r\nCAN1 receive data: \r\n");
            for(i = 0U; i < receive_message.data_bytes; i++) {
                printf("%02x ", receive_message.data[i]);
            }
            gd_eval_led_toggle(LED3);
        }
    }
}

2.
void CAN1_Message_IRQHandler(void)
{
    if(RESET != can_interrupt_flag_get(CAN1, CAN_INT_FLAG_MB0)) {
        /* read the receive message */
        can_mailbox_receive_data_read(CAN1, 0U, &receive_message);
        can1_receive_flag = SET;
    }
}
____________________________________________________________________________________________________________________________
______________________LPDTS____________________________________________________________________________________________________
Fix file:
../Examples/LPDTS/LXTAL_measure_with_calibration/main.c
../Examples/LPDTS/PCLK_measure_with_interrupt_mode/main.c

fix reason: Bug Fix. 

V1.2.0:
int main(void)
{
    ......
    temperature = lpdts_temperature_get();

    /* infinite loop */ 
    while(1) {
        delay_1ms(1000);
        printf("The temperature is %d degrees Celsius now.\r\n", temperature);
    }
}

V1.3.0:
int main(void)
{
    ......
    ret = lpdts_temperature_get(&temperature);

    /* infinite loop */ 
    while(1) {
        delay_1ms(1000);
        if(ret == SUCCESS){
            printf("The temperature is %d degrees Celsius now.\r\n", temperature);
        } else {
            printf("Get temperature failed.\r\n");
        }
    }
}
_____________________________________________________________________________________________________________________________
______________________LPDTS____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_lpdts.h
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_lpdts.c

fix reason: Bug Fix. 

V1.2.0:
int32_t lpdts_temperature_get(void)
{
    uint32_t freq;
    uint32_t count;
    int32_t t0;
    uint32_t val;
    uint32_t t0_freq;
    uint32_t ramp_coeff;
    uint32_t reg_cfg;
    int32_t temperature;

    /* get the total number of samples */
    count = (LPDTS_DATA & LPDTS_DATA_COVAL);
    /* get LPDTS_CFG configuration */
    reg_cfg = LPDTS_CFG;

    /* get the module frequency on Hz */
    if((reg_cfg & LPDTS_CFG_REFSEL) == LPDTS_CFG_REFSEL) {
        freq = (LXTAL_VALUE * count) / (2U * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET));
    } else {
        freq = (2U * rcu_clock_freq_get(CK_APB1) / count) * ((reg_cfg & LPDTS_CFG_SPT) >> LPDTS_CFG_SPT_OFFSET);
    }

    /* read factory settings */
    val = (LPDTS_SDATA & LPDTS_SDATA_VAL) >> LPDTS_SDATA_VAL_OFFSET;
    if(val == 0U) {
        t0 = LPDTS_T0_TMP_VAL0;
    } else if(val == 1U) {
        t0 = LPDTS_T0_TMP_VAL1;
    }

    /* get the T0 frequency on Hz */
    t0_freq = (LPDTS_SDATA & LPDTS_SDATA_FREQ) * 100U;
    /* get the ramp coefficient for the temperature sensor on deg C/Hz */
    ramp_coeff = LPDTS_RDATA & LPDTS_RDATA_RCVAL;

    /* figure out the temperature deg C */
    temperature = t0 + (((int32_t)freq - (int32_t)t0_freq) / (int32_t)ramp_coeff);

    return temperature;
}

V1.3.0:
ErrStatus lpdts_temperature_get(int32_t* temperature)
{
    uint32_t freq;
    uint32_t count;
    int32_t t0 = 0;
    uint32_t val;
    uint32_t t0_freq;
    uint32_t ramp_coeff;
    uint32_t reg_cfg;
    ErrStatus ret = SUCCESS;
    /* get the total number of samples */
    count = (LPDTS_DATA & LPDTS_DATA_COVAL);
    /* get LPDTS_CFG configuration */
    reg_cfg = LPDTS_CFG;

    if((reg_cfg & LPDTS_CFG_REFSEL) == LPDTS_CFG_REFSEL) {
        freq = (LXTAL_VALUE * count) / ((reg_cfg & LPDTS_CFG_SPT) >> 15U); /* On Hz */
    } else {
        freq = (2U * rcu_clock_freq_get(CK_APB1) / count) * ((reg_cfg & LPDTS_CFG_SPT) >> 16U) ; /* On Hz */
    }
    /* read factory settings */
    val = (LPDTS_SDATA & LPDTS_SDATA_VAL) >> 16U;
    if(val == 0U) {
        t0 = 25; /* 25 deg C */
    } else if(val == 1U){
        t0 = -40; /* -40 deg C */
    } else {
        ret = ERROR;
    }
    
    t0_freq = (LPDTS_SDATA & LPDTS_SDATA_FREQ) * 100U; /* Hz */
    ramp_coeff = LPDTS_RDATA & LPDTS_RDATA_RCVAL; /* HZ/deg C */
    /* figure out the temperature deg C */
    *temperature = t0 + (((int32_t)freq - (int32_t)t0_freq) / (int32_t)ramp_coeff);
    
    return ret;
}
_____________________________________________________________________________________________________________________________
_____________________USBHS____________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_usbhs_library/device/class/iap/Source/usb_iap_core.c
../Examples/USBHS/usb_device/in_application_program_hid/src/flash_operation.c

fix reason: Bug Fix. Resolve the IAP download bug.

V1.2.0:
1.
static void iap_req_leave(usb_dev *udev)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* get base address to jump */
    iap->base_address  = iap->report_buf[2];
    iap->base_address |= (uint32_t)iap->report_buf[3] << 8;
    iap->base_address |= (uint32_t)iap->report_buf[4] << 16;
    iap->base_address |= (uint32_t)iap->report_buf[5] << 24;

    iap->dev_status[0] = IAP_DEVICE_ID;
    iap->dev_status[1] = LEAVE_FINISH;

    usbd_ep_send(udev, IAP_IN_EP, iap->dev_status, IAP_IN_PACKET);

    usb_mdelay(3U);
    usbd_disconnect(udev);
    rcu_deinit();
    jump_to_execute(iap->base_address);

}

2.
fmc_state_enum iap_data_write(uint8_t *data, uint32_t addr, uint32_t len)
{
    uint32_t idx = 0U;
    fmc_state_enum fmc_state = FMC_READY;

    /* check if the address is in protected area */
    if(IS_PROTECTED_AREA(addr)) {
        return fmc_state;
    }

    if(len & 0x03U) {/* not an aligned data */
        for(idx = len; idx < ((len & 0xFFFCU) + 4U); idx++) {
            data[idx] = 0xFFU;
        }
    }

   /* unlock the flash program erase controller */
    fmc_unlock();

    /* data received are word multiple */
    for(idx = 0U; idx < len; idx += 4U) {
        fmc_state = fmc_word_program(addr, *(uint32_t *)(data + idx));

        if(FMC_READY == fmc_state) {
            addr += 4U;
        } else {
            while(1) {
            }
        }
    }

    fmc_lock();

    return fmc_state;
}

V1.3.0:
1.
static void iap_req_leave(usb_dev *udev)
{
    usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE];

    /* get base address to jump */
    iap->base_address  = iap->report_buf[2];
    iap->base_address |= (uint32_t)iap->report_buf[3] << 8;
    iap->base_address |= (uint32_t)iap->report_buf[4] << 16;
    iap->base_address |= (uint32_t)iap->report_buf[5] << 24;

    iap->dev_status[0] = IAP_DEVICE_ID;
    iap->dev_status[1] = LEAVE_FINISH;

    usbd_ep_send(udev, IAP_IN_EP, iap->dev_status, IAP_IN_PACKET);

    usb_mdelay(3U);
    usbd_disconnect(udev);
  
    NVIC_SystemReset();
    jump_to_execute(iap->base_address);

}
2.
fmc_state_enum iap_data_write(uint8_t *data, uint32_t addr, uint32_t len)
{
    uint32_t idx = 0U;
    fmc_state_enum fmc_state = FMC_READY;

    /* check if the address is in protected area */
    if(IS_PROTECTED_AREA(addr)) {
        return fmc_state;
    }

    if(len & 0x03U) {/* not an aligned data */
        for(idx = len; idx < ((len & 0xFFFCU) + 4U); idx++) {
            data[idx] = 0xFFU;
        }
    }

   /* unlock the flash program erase controller */
    fmc_unlock();

    /* data received are word multiple */
    for(idx = 0U; idx < len; idx += 4U) {
        fmc_state = fmc_word_program(addr, *(uint32_t *)(data + idx));

        if(FMC_READY == fmc_state) {
            addr += 4U;
        } else {
            addr += 4U;
            fmc_flag_clear(FMC_FLAG_PGSERR);
            fmc_flag_clear(FMC_FLAG_WPERR);
            fmc_flag_clear(FMC_FLAG_END);
            fmc_state = FMC_READY;
        }
    }

    fmc_lock();

    return fmc_state;
}
_____________________________________________________________________________________________________________________________

******************* V1.2.0 2025-08-07 ******************************************************************************************
______________________Common_________________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32H75E/Include/gd32h75e_err_report.h

fix reason: Bug Fix. change HSM_ERR_REPORT_H to ERR_REPORT_H

V1.1.0:
#ifndef HSM_ERR_REPORT_H
#define HSM_ERR_REPORT_H

V1.2.0:
#ifndef ERR_REPORT_H
#define ERR_REPORT_H
__________________________________________________________________________________________________________________________
______________________Common_________________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32H75E/Source/system_gd32h75e.c

fix reason: Fix the issue where the enum_speed parameter may cause an array out-of-bounds error.

V1.1.0:
1.
#include "gd32h75e.h"
2.
void SystemInit(void)
{
    ......
    /* enable IRC64M */
    RCU_CTL |= RCU_CTL_IRC64MEN;
    while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
    }

    /* no TCM wait state */
    RCU_APB4EN |= RCU_APB4EN_SYSCFG;
    SYSCFG_SRAMCFG1 &= ~SYSCFG_SRAMCFG1_TCM_WAITSTATE;
    ......
}

V1.2.0:
1.
#include "gd32h75e.h"
#ifdef GD32H75E_ESC
#include "gd32h75e_esc_ospi.h"
#include "gd32h75e_esc_gpio.h"
#include "gd32h75e_esc_rcu.h"
#include "gd32h75e_esc_pmu.h"
#include "gd32h75e_esc_syscfg.h"
#endif /* GD32H75E_ESC */

2. 
void SystemInit(void)
{
    /* enable IRC64M */
    RCU_CTL |= RCU_CTL_IRC64MEN;
    while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
    }

    /* disable oe_ext clock output */
    esc_oeext_clock_disable();
    /* no TCM wait state */
    RCU_APB4EN |= RCU_APB4EN_SYSCFG;
    SYSCFG_SRAMCFG1 &= ~SYSCFG_SRAMCFG1_TCM_WAITSTATE;
}

3. 
Add function esc_oeext_clock_disable.

4. Add 
#ifdef GD32H75E_ESC
/* disable oe_ext clock output */
static ErrStatus esc_oeext_clock_disable(void);
#endif /* GD32H75E_ESC */
__________________________________________________________________________________________________________________________
______________________I2C_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_i2c.c
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_i2c.h

fix reason: Bug Fix. Change the byte_number parameter type in the function from uint32_t to uint8_t.

V1.1.0:
i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number)

V1.2.0:
i2c_transfer_byte_number_config(uint32_t i2c_periph, uint8_t byte_number)
__________________________________________________________________________________________________________________________
______________________I2C_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_i2c.c
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_i2c.h

fix reason: Delete function. 

V1.1.0:

V1.2.0:
Delete function i2c_nack_disable.
__________________________________________________________________________________________________________________________
______________________PMU_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_pmu.c

fix reason: Bug Fix.

V1.1.0:
void pmu_to_standbymode(void)
{
    /* set stbmod bit */
    PMU_CTL0 |= PMU_CTL0_STBMOD;

    /* reset wakeup flag */
    PMU_CTL0 |= PMU_CTL0_WURST;

    /* set sleepdeep bit of Cortex-M7 system control register */
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

    REG32(0xE000E010U) &= 0x00010004U;
    REG32(0xE000E180U)  = 0xFF87FFF3U;
    REG32(0xE000E184U)  = 0x8FFFFDFFU;
    REG32(0xE000E188U)  = 0x9FFFFFF0U;
    REG32(0xE000E18CU)  = 0xB577C043U;
    REG32(0xE000E190U)  = 0x07C30200U;
    REG32(0xE000E194U)  = 0xFFFBFFFEU;
    REG32(0xE000E198U)  = 0x01FFFFFFU;

    /* enter standby mode */
    __WFI();
}

V1.2.0:
void pmu_to_standbymode(void)
{
    /* set stbmod bit */
    PMU_CTL0 |= PMU_CTL0_STBMOD;

    /* reset wakeup flag */
    PMU_CTL0 |= PMU_CTL0_WURST;

    /* set sleepdeep bit of Cortex-M7 system control register */
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

    REG32(0xE000E010U) &= 0x00010004U;
    REG32(0xE000E180U)  = 0xFF87FFFFU;
    REG32(0xE000E184U)  = 0x1FFDFBFFU;
    REG32(0xE000E188U)  = 0x907F3FF0U;
    REG32(0xE000E18CU)  = 0x8473C041U;
    REG32(0xE000E190U)  = 0x06430200U;
    REG32(0xE000E194U)  = 0xFFFBFFE6U;
    REG32(0xE000E198U)  = 0x007FFFFFU;

    /* enter standby mode */
    __WFI();
}
__________________________________________________________________________________________________________________________
______________________PMU_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_pmu.h

fix reason: Bug Fix. Modify the values of LVDT.

V1.1.0:
#define PMU_LVDT_0                      CTL0_LVDT(0)                        /*!< voltage threshold is 2.1V */
#define PMU_LVDT_1                      CTL0_LVDT(1)                        /*!< voltage threshold is 2.3V */
#define PMU_LVDT_2                      CTL0_LVDT(2)                        /*!< voltage threshold is 2.4V */
#define PMU_LVDT_3                      CTL0_LVDT(3)                        /*!< voltage threshold is 2.6V */
#define PMU_LVDT_4                      CTL0_LVDT(4)                        /*!< voltage threshold is 2.7V */
#define PMU_LVDT_5                      CTL0_LVDT(5)                        /*!< voltage threshold is 2.9V */
#define PMU_LVDT_6                      CTL0_LVDT(6)                        /*!< voltage threshold is 3.0V */

V1.2.0:
#define PMU_LVDT_0                      CTL0_LVDT(0)                        /*!< voltage threshold is 1.90V */
#define PMU_LVDT_1                      CTL0_LVDT(1)                        /*!< voltage threshold is 2.05V */
#define PMU_LVDT_2                      CTL0_LVDT(2)                        /*!< voltage threshold is 2.20V */
#define PMU_LVDT_3                      CTL0_LVDT(3)                        /*!< voltage threshold is 2.35V */
#define PMU_LVDT_4                      CTL0_LVDT(4)                        /*!< voltage threshold is 2.50V */
#define PMU_LVDT_5                      CTL0_LVDT(5)                        /*!< voltage threshold is 2.65V */
#define PMU_LVDT_6                      CTL0_LVDT(6)                        /*!< voltage threshold is 2.80V */
__________________________________________________________________________________________________________________________
______________________ESC_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_esc_library/Include/gd32h75e_esc_syscfg.h

fix reason: Bug Fix. 

V1.1.0:
#define ESC_OPB_CS                          (ESC_CCTL_REG_BASE_ADDR+ESC_OPB_CS_OFFSE)           /* ESC_OPB_CS register */

V1.2.0:
#define ESC_OPB_CS                          (ESC_CCTL_REG_BASE_ADDR+ESC_OPB_CS_OFFSET)           /* ESC_OPB_CS register */
__________________________________________________________________________________________________________________________
______________________ESC_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_esc_library/Source/gd32h75e_esc_phy.c

fix reason: Bug Fix. 

V1.1.0:

V1.2.0:
1. Modify function esc_phy_read and esc_phy_write, add static function phy_pdi_read and phy_pdi_write.
2. Add parameter check function.
__________________________________________________________________________________________________________________________
______________________MDMA_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_mdma.c

fix reason: Bug Fix. 

V1.1.0:
1. 
#define STAT1_FLAG_MASK             ((uint32_t)0x0000F000U)                 /*!< MDMA_STAT1 flag mask */
2.
        if(UPDATE_DIR_DECREASE == block_init_struct->saddr_update_val) {
            node->chxbtcfg_reg |= MDMA_CHXBTCFG_SADDRUM;
            /* write new chxmbaddru register value: source repeat block offset */
            blockoffset = (uint32_t)block_init_struct->saddr_update_val;
            node->chxmbaddru_reg |= (blockoffset & MDMA_ADDRESS_MASK);
        } else {
            node->chxbtcfg_reg &= ~MDMA_CHXBTCFG_SADDRUM;
            /* write new chxmbaddru register value: source repeat block offset */
            node->chxmbaddru_reg |= (((uint32_t)block_init_struct->saddr_update_val) & MDMA_ADDRESS_MASK);
        }

V1.2.0:
1. 
#define STAT1_FLAG_MASK             ((uint32_t)0x00000F00U)                 /*!< MDMA_STAT1 flag mask */
2.
        if(UPDATE_DIR_DECREASE == block_init_struct->saddr_update_dir) {
            node->chxbtcfg_reg |= MDMA_CHXBTCFG_SADDRUM;
            /* write new chxmbaddru register value: source repeat block offset */
            blockoffset = (uint32_t)block_init_struct->saddr_update_val;
            node->chxmbaddru_reg |= (blockoffset & MDMA_ADDRESS_MASK);
        } else {
            node->chxbtcfg_reg &= ~MDMA_CHXBTCFG_SADDRUM;
            /* write new chxmbaddru register value: source repeat block offset */
            node->chxmbaddru_reg |= (((uint32_t)block_init_struct->saddr_update_val) & MDMA_ADDRESS_MASK);
        }
__________________________________________________________________________________________________________________________
______________________HPDF_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_hpdf.c

fix reason: Bug Fix. 

V1.1.0:
void hpdf_clock_output_config(uint32_t source, uint8_t divider, uint32_t mode)
{
#ifdef FW_DEBUG_ERR_REPORT
    if(NOT_HPDFCLK_SOURCE(source)) {
        fw_debug_report_err(SYSCFG_MODULE_ID, API_ID(12), ERR_PARAM_INVALID);
    } else if(NOT_CKOUT_MOD(mode)) {
        fw_debug_report_err(SYSCFG_MODULE_ID, API_ID(12), ERR_PARAM_INVALID);
    } else
#endif /* FW_DEBUG_ERR_REPORT */
    {
        uint32_t reg;
        reg = HPDF_CHXCTL(CHANNEL0);
        reg &= ~(HPDF_CH0CTL_CKOUTSEL | HPDF_CH0CTL_CKOUTSEL | HPDF_CH0CTL_CKOUTDM);
        /* configure serial output clock */
        reg |= (source | ((uint32_t)divider << CH0CTL_CKOUTDIV_OFFSET) | mode);
        HPDF_CHXCTL(CHANNEL0) = reg;
    }
}

V1.2.0:
void hpdf_clock_output_config(uint32_t source, uint8_t divider, uint32_t mode)
{
#ifdef FW_DEBUG_ERR_REPORT
    if(NOT_HPDFCLK_SOURCE(source)) {
        fw_debug_report_err(SYSCFG_MODULE_ID, API_ID(12), ERR_PARAM_INVALID);
    } else if(NOT_CKOUT_MOD(mode)) {
        fw_debug_report_err(SYSCFG_MODULE_ID, API_ID(12), ERR_PARAM_INVALID);
    } else
#endif /* FW_DEBUG_ERR_REPORT */
    {
        uint32_t reg;
        reg = HPDF_CHXCTL(CHANNEL0);
        reg &= ~(HPDF_CH0CTL_CKOUTSEL | HPDF_CH0CTL_CKOUTDIV | HPDF_CH0CTL_CKOUTDM);
        /* configure serial output clock */
        reg |= (source | ((uint32_t)divider << CH0CTL_CKOUTDIV_OFFSET) | mode);
        HPDF_CHXCTL(CHANNEL0) = reg;
    }
}
__________________________________________________________________________________________________________________________
______________________PMU_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_pmu.c

fix reason: Bug Fix. 

V1.1.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
#ifdef FW_DEBUG_ERR_REPORT
    if(NOT_PMU_SLEEPMODE(sleepmodecmd)) {
        fw_debug_report_err(PMU_MODULE_ID, API_ID(0x0016U), ERR_PARAM_INVALID);
    } else
#endif /* FW_DEBUG_ERR_REPORT */
    {
        /* clear sleepdeep bit of Cortex-M7 system control register */
        SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

        /* select WFI or WFE command to enter sleep mode */
        if(WFI_CMD == sleepmodecmd) {
            __WFI();
        } else {
            __WFE();
            __WFE();
        }
    }
}

V1.2.0:
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
#ifdef FW_DEBUG_ERR_REPORT
    if(NOT_PMU_SLEEPMODE(sleepmodecmd)) {
        fw_debug_report_err(PMU_MODULE_ID, API_ID(0x0016U), ERR_PARAM_INVALID);
    } else
#endif /* FW_DEBUG_ERR_REPORT */
    {
        /* clear sleepdeep bit of Cortex-M7 system control register */
        SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);

        /* select WFI or WFE command to enter sleep mode */
        if(WFI_CMD == sleepmodecmd) {
            __WFI();
        } else {
			__SEV();
            __WFE();
            __WFE();
        }
    }
}
__________________________________________________________________________________________________________________________
______________________USART_________________________________________________________________________________________________
Fix file:
../Examples/USART/Half_duplex_transmitter&receiver/main.c

fix reason: Bug Fix. Modify the TX pin to open-drain output.

V1.1.0:
    /* configure USART0 TX as alternate function push-pull */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_100_220MHZ, GPIO_PIN_9);
    /* configure USART1 TX as alternate function push-pull */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_100_220MHZ, GPIO_PIN_2);

V1.2.0:
    /* configure USART0 TX as alternate function open drain */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_100_220MHZ, GPIO_PIN_9);
    /* configure USART1 TX as alternate function open drain */
    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_100_220MHZ, GPIO_PIN_2);
__________________________________________________________________________________________________________________________
______________________RAMECCMU_________________________________________________________________________________________________
Fix file:
../Examples/RAMECCMU/Single_ECC_error_handle/gd32h75e_it.h
../Examples/RAMECCMU/Single_ECC_error_handle/gd32h75e_it.c

fix reason: Modify ECC_IRQHandler to RAMECCMU_IRQHandler.

for example
V1.1.0:
ECC_IRQHandler

V1.2.0:
RAMECCMU_IRQHandler
__________________________________________________________________________________________________________________________
______________________ESC_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_esc_library/Source/gd32h75e_esc_ospi.c


fix reason: Modify function ospi_write_pdram and ospi_read_pdram.

V1.1.0:
static void ospi_write_pdram(uint8_t *writebuffer, uint16_t address, uint16_t count, uint32_t ospi_periph, ospi_parameter_struct *ospi_struct,
                            interface_mode mode, uint8_t write_cmd, uint8_t read_cmd, addr_inc_mode inc_mode)
{
    ......
    if(0U < count) {
        if((count % 4U) == 1U)
            ospi_write(ospi_periph, ospi_struct, mode, write_cmd, inc_mode,
                       ESC_PRAM_FIFO_DW, (writebuffer + i), count + 3U);
        else if((count % 4U) == 2U)
            ospi_write(ospi_periph, ospi_struct, mode, write_cmd, inc_mode,
                       ESC_PRAM_FIFO_DW, (writebuffer + i), count + 2U);
        else if((count % 4U) == 3U)
            ospi_write(ospi_periph, ospi_struct, mode, write_cmd, inc_mode,
                       ESC_PRAM_FIFO_DW, (writebuffer + i), count + 1U);
        else
            ospi_write(ospi_periph, ospi_struct, mode, write_cmd, inc_mode,
                       ESC_PRAM_FIFO_DW, (writebuffer + i), count);
    }
    return;
}

static void ospi_read_pdram(uint8_t *readbuffer, uint16_t address, uint16_t count, uint32_t ospi_periph, ospi_parameter_struct *ospi_struct,
                           interface_mode mode, uint8_t write_cmd, uint8_t read_cmd, addr_inc_mode inc_mode)
{
    ......
    if(0U < count) {
        if((count % 4U) == 1U)
            ospi_read(ospi_periph, ospi_struct, mode, read_cmd, inc_mode,
                      ESC_PRAM_FIFO_DR, (readbuffer + i), count + 3U);
        else if((count % 4U) == 2U)
            ospi_read(ospi_periph, ospi_struct, mode, read_cmd, inc_mode,
                      ESC_PRAM_FIFO_DR, (readbuffer + i), count + 2U);
        else if((count % 4U) == 3U)
            ospi_read(ospi_periph, ospi_struct, mode, read_cmd, inc_mode,
                      ESC_PRAM_FIFO_DR, (readbuffer + i), count + 1U);
        else
            ospi_read(ospi_periph, ospi_struct, mode, read_cmd, inc_mode,
                      ESC_PRAM_FIFO_DR, (readbuffer + i), count);
    }
    return;
}

V1.2.0:
static void ospi_write_pdram(uint8_t *writebuffer, uint16_t address, uint16_t count, uint32_t ospi_periph, ospi_parameter_struct *ospi_struct,
                            interface_mode mode, uint8_t write_cmd, uint8_t read_cmd, addr_inc_mode inc_mode)
{
    ......
	while(count) {
        nlength = count > 4 ? 4 : count;
        param32_1.Val = 0;
        memcpy(&param32_1, (writebuffer + i), nlength);

            ospi_write(ospi_periph, ospi_struct, mode, write_cmd, inc_mode,
               ESC_PRAM_FIFO_DW, &param32_1.v[0], 4U);

        i += nlength;
        count -= nlength;
        nWrtSpcAvlCount--;
    }

    return;
}

static void ospi_read_pdram(uint8_t *readbuffer, uint16_t address, uint16_t count, uint32_t ospi_periph, ospi_parameter_struct *ospi_struct,
                           interface_mode mode, uint8_t write_cmd, uint8_t read_cmd, addr_inc_mode inc_mode)
{
    ......
	while(count) {
            ospi_read(ospi_periph, ospi_struct, mode, read_cmd, inc_mode,
              ESC_PRAM_FIFO_DR, &param32_1.v[0], 4U);
        nlength = count > 4 ? 4 : count;
        memcpy((readbuffer + i), &param32_1, nlength);
        i += nlength;
        count -= nlength;
        nReadSpaceAvblCount--;
    }

    return;
}
__________________________________________________________________________________________________________________________
______________________ESC_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_esc_library/Source/gd32h75e_esc_syscfg.c

fix reason: Delete function syscfg_efuse_read.

V1.1.0:

V1.2.0:
Delete function syscfg_efuse_read
__________________________________________________________________________________________________________________________
______________________ESC_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_esc_library/Source/gd32h75e_esc_ospi.c
../Firmware/GD32H75E_esc_library/Include/gd32h75e_esc_ospi.h

fix reason: Modify the function implementation. Delete function ospi_enable_qspi_mode.

V1.1.0:
1. 
void ospi_write(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, interface_mode mode, uint8_t cmd, addr_inc_mode inc_mode,
                uint32_t addr, uint8_t *pdata, uint32_t data_size)
2.
void ospi_read(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, interface_mode mode, uint8_t cmd, addr_inc_mode inc_mode,
               uint32_t addr, uint8_t *pdata, uint32_t data_size)
3. 
void ospi_write_reg(uint8_t *writebuffer, uint16_t address, uint8_t count, uint32_t ospi_periph, ospi_parameter_struct *ospi_struct,
                          interface_mode mode, uint8_t write_cmd, uint8_t read_cmd, addr_inc_mode inc_mode)
4.
void ospi_read_reg(uint8_t *readbuffer, uint16_t address, uint8_t count, uint32_t ospi_periph, ospi_parameter_struct *ospi_struct,
                         interface_mode mode, uint8_t write_cmd, uint8_t read_cmd, addr_inc_mode inc_mode)
5.
static void ospi_write_pdram(uint8_t *writebuffer, uint16_t address, uint16_t count, uint32_t ospi_periph, ospi_parameter_struct *ospi_struct,
                            interface_mode mode, uint8_t write_cmd, uint8_t read_cmd, addr_inc_mode inc_mode)
6.
static void ospi_read_pdram(uint8_t *readbuffer, uint16_t address, uint16_t count, uint32_t ospi_periph, ospi_parameter_struct *ospi_struct,
                           interface_mode mode, uint8_t write_cmd, uint8_t read_cmd, addr_inc_mode inc_mode)

V1.2.0:
1.
void ospi_write(ospi_parameter_struct *ospi_struct, uint32_t addr, uint8_t *pdata, uint32_t data_size)
2.
void ospi_read(ospi_parameter_struct *ospi_struct, uint32_t addr, uint8_t *pdata, uint32_t data_size)
3.
static void ospi_write_reg(uint8_t *writebuffer, uint16_t address, uint8_t count, ospi_parameter_struct *ospi_struct)
4.
static void ospi_read_reg(uint8_t *readbuffer, uint16_t address, uint8_t count, ospi_parameter_struct *ospi_struct)
5.
static void ospi_write_pdram(uint8_t *writebuffer, uint16_t address, uint16_t count, ospi_parameter_struct *ospi_struct)
6.
static void ospi_read_pdram(uint8_t *readbuffer, uint16_t address, uint16_t count, ospi_parameter_struct *ospi_struct)
7.
Delete function ospi_enable_qspi_mode.
__________________________________________________________________________________________________________________________
______________________ESC_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_esc_library/Include/gd32h75e_esc_syscfg.h
../Firmware/GD32H75E_esc_library/Source/gd32h75e_esc_intc.c
../Firmware/GD32H75E_esc_library/Source/gd32h75e_esc_phy.c
../Firmware/GD32H75E_esc_library/Source/gd32h75e_esc_pmu.c
../Firmware/GD32H75E_esc_library/Source/gd32h75e_esc_syscfg.c
../Firmware/GD32H75E_esc_library/Source/gd32h75e_esc_timer.c
../Examples/ESC/ESC_Template/main.c
../Examples/ESC/ESC_TIMER/esc_basic_timer_interrupt/main.c
../Examples/ESC/ESC_PMU/Byte_test_and_wait _module_ready/main.c
../Examples/ESC/ESC_PHY/esc_internal_phy_read_write/main.c
../Examples/ESC/ESC_INTC/Device_ready_interrupt_mode/main.c
../Examples/ESC/ESC_INTC/Clock_output_test_mode/main.c

fix reason: Modify according the modification of the function in gd32h75e_esc_ospi.c.

for example
V1.1.0:
    ospi_read(OSPI_INTERFACE, &ospi_init_struct, MODE_SELECT,CMD_READ, ADDR_NO_INC, PMU_PDIREFVAL, (uint8_t*)&temp, 4U);
V1.2.0:
    ospi_read(&ospi_init_struct, PMU_PDIREFVAL, (uint8_t*)&temp, 4U);
__________________________________________________________________________________________________________________________
______________________USB_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_usbhs_library/driver/Source/drv_usb_dev.c

fix reason: Fix the issue where the enum_speed parameter may cause an array out-of-bounds error.

V1.1.0:
usb_status usb_transc0_active(usb_core_driver *udev, usb_transc *transc)
{
    ......
    uint32_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES;
    ......
}
V1.2.0:
usb_status usb_transc0_active(usb_core_driver *udev, usb_transc *transc)
{
    ......
    uint32_t enum_speed = ((udev->regs.dr->DSTAT & DSTAT_ES) >> 1);
    ......
}
__________________________________________________________________________________________________________________________
______________________FMC_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_fmc.h
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_fmc.c

fix reason:  Add Function. Delete ob_tcm_shared_ram_size_get, ADD ob_itcm_shared_ram_size_get and ob_dtcm_shared_ram_size_get.

V1.1.0:
void ob_tcm_shared_ram_size_get(uint32_t *itcm_shared_ram_kb_size, uint32_t *dtcm_shared_ram_kb_size);

V1.2.0:
uint32_t ob_itcm_shared_ram_size_get(void);
uint32_t ob_dtcm_shared_ram_size_get(void);
__________________________________________________________________________________________________________________________
______________________CAN_________________________________________________________________________________________________
Fix file:
../Examples/CAN/communication_FDmode/main.c

fix reason:  Add Function. The frequency division coefficients of the arbitration domain and the data domain of the CANFD frame remain consistent.

V1.1.0:
void can_config(void)
{
    ......
    /* baud rate 500Kbps, sample point at 80% */
    can_parameter.resync_jump_width = 1U;
    can_parameter.prop_time_segment = 2U;
    can_parameter.time_segment_1 = 5U;
    can_parameter.time_segment_2 = 2U;
    can_parameter.prescaler = 60U;

    ......
    fd_parameter.tdc_enable = ENABLE;
    fd_parameter.tdc_offset = 2U;
    /* FD baud rate 1Mbps, sample point at 80% */
    fd_parameter.resync_jump_width = 1U;
    fd_parameter.prop_time_segment = 2U;
    fd_parameter.time_segment_1 = 5U;
    fd_parameter.time_segment_2 = 2U;
    fd_parameter.prescaler = 30U;
}

V1.2.0:
void can_config(void)
{
    ......
    /* baud rate 1Mbps, sample point at 80% */
    can_parameter.resync_jump_width = 1U;
    can_parameter.prop_time_segment = 5U;
    can_parameter.time_segment_1 = 10U;
    can_parameter.time_segment_2 = 4U;
    can_parameter.prescaler = 15U;

    ......
    fd_parameter.tdc_enable = DISABLE;
    fd_parameter.tdc_offset = 2U;
    /* FD baud rate 2Mbps, sample point at 80% */
    fd_parameter.resync_jump_width = 1U;
    fd_parameter.prop_time_segment = 2U;
    fd_parameter.time_segment_1 = 5U;
    fd_parameter.time_segment_2 = 2U;
    fd_parameter.prescaler = 15U;
}
__________________________________________________________________________________________________________________________
______________________USB_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_usbhs_library/device/core/Source/usbd_core.c

fix reason: Bug Fix. Modify the firmware library and pass the self-powered CVTest.

V1.1.0:
void usbd_init(usb_core_driver *udev, usb_desc *desc, usb_class_core *class_core)
{
    ......
    /* create serial string */
    serial_string_get(udev->dev.desc->strings[STR_IDX_SERIAL]);

    /* configure USB capabilities */
    (void)usb_basic_init(&udev->bp, &udev->regs);
    ......
}

V1.2.0:
void usbd_init(usb_core_driver *udev, usb_desc *desc, usb_class_core *class_core)
{
    ......
    /* create serial string */
    serial_string_get(udev->dev.desc->strings[STR_IDX_SERIAL]);

    /* configure power management */
    udev->dev.pm.power_mode = (udev->dev.desc->config_desc[7] & BIT(6)) >> 6;

    /* configure USB capabilities */
    (void)usb_basic_init(&udev->bp, &udev->regs);
    ......
}
_________________________________________________________________________________________________________________________
______________________USB_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_usbhs_library/device/core/Source/usbd_enum.c

fix reason: Bug Fix. Modify the firmware library and pass the self-powered CVTest.

V1.1.0:
static uint8_t *_usb_str_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len)
{
    ......
    if(udev->dev.pm.dev_remote_wakeup) {
        status[0] |= USB_STATUS_REMOTE_WAKEUP;
    } else {
        status[0] = 0U;
    }
    ......
}

V1.2.0:
static uint8_t *_usb_str_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len)
{
    ......
    if(udev->dev.pm.dev_remote_wakeup) {
        status[0] |= USB_STATUS_REMOTE_WAKEUP;
    }
    ......
}
_________________________________________________________________________________________________________________________
______________________USB_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_usbhs_library/device/core/Source/usbd_enum.c
../Firmware/GD32H75E_usbhs_library/device/core/Source/usbd_core.c

fix reason: Bug Fix. Modify the firmware library and pass the self-powered CVTest.

V1.1.0:
1.
void usbd_init(usb_core_driver *udev, usb_desc *desc, usb_class_core *class_core)
{
    ......
    /* create serial string */
    serial_string_get(udev->dev.desc->strings[STR_IDX_SERIAL]);

    /* configure USB capabilities */
    (void)usb_basic_init(&udev->bp, &udev->regs);
    ......
}

V1.2.0:
1.
void usbd_init(usb_core_driver *udev, usb_desc *desc, usb_class_core *class_core)
{
    ......
    /* create serial string */
    serial_string_get(udev->dev.desc->strings[STR_IDX_SERIAL]);

    /* configure power management */
    udev->dev.pm.power_mode = (udev->dev.desc->config_desc[7] & BIT(6)) >> 6;

    /* configure USB capabilities */
    (void)usb_basic_init(&udev->bp, &udev->regs);
    ......
}
_________________________________________________________________________________________________________________________
______________________USB_________________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_usbhs_library/driver/Source/drv_usbh_int.c

fix reason: Bug Fix. Delete the redundant usb_pp_halt function.

V1.1.0:
static uint32_t usbh_int_pipe_out(usb_core_driver *udev, uint32_t pp_num)
{
    ......
        pp->err_count = 0U;
        if(USB_USE_FIFO == udev->bp.transfer_mode) {
            usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK);
        } else {
            pp_reg->HCHINTF = HCHINTF_NAK;
        }
        usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK);
    } else if(intr_pp & HCHINTF_USBER) {
    ......
}

V1.2.0:
static uint32_t usbh_int_pipe_out(usb_core_driver *udev, uint32_t pp_num)
{
    ......
        pp->err_count = 0U;
        if(USB_USE_FIFO == udev->bp.transfer_mode) {
            usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK);
        } else {
            pp_reg->HCHINTF = HCHINTF_NAK;
        }
    } else if(intr_pp & HCHINTF_USBER) {
    ......
}
_________________________________________________________________________________________________________________________
______________________SPI_________________________________________________________________________________________________
Fix file:
../Examples/SPI/SPI_master_slave_fullduplex_dma/main.c
../Examples/SPI/SPI_master_slave_fullduplex_polling/main.c
../Examples/SPI/SPI_master_slave_fullduplex_polling_dp/main.c

fix reason: Bug Fix.

V1.1.0:
void spi_config(void)
{
    ......
    /* enable SPI NSS output */
    spi_nss_output_enable(SPI0);
}

V1.2.0:
void spi_config(void)
{
    ......
    /* SPI NSS pin high level in software mode */
    spi_nss_internal_high(SPI0);
}
_________________________________________________________________________________________________________________________
______________________SPI_________________________________________________________________________________________________
Fix file:
../Examples/SPI/SPI_master_transmit_slave_receive_interrupt/main.c

fix reason: Bug Fix.

V1.1.0:
void spi_config(void)
{
    ......
    /* SPI NSS pin low level in software mode */
    spi_nss_internal_low(SPI0);
    spi_nss_internal_low(SPI1);

    /* enable SPI NSS output */
    spi_nss_output_enable(SPI0);
}

V1.2.0:
void spi_config(void)
{
    ......
    /* SPI NSS pin high level in software mode */
    spi_nss_internal_high(SPI0);
}
_________________________________________________________________________________________________________________________
______________________SPI_________________________________________________________________________________________________
Fix file:
../Examples/SPI/I2S_master_transmit_slave_receive_dma/main.c
../Examples/SPI/SPI_master_slave_fullduplex_dma/main.c
../Examples/SPI/SPI_master_slave_fullduplex_polling/main.c
../Examples/SPI/SPI_master_slave_fullduplex_polling_dp/main.c
../Examples/SPI/SPI_master_slave_fullduplex_ti_mode/main.c
../Examples/SPI/SPI_master_transmit_slave_receive_interrupt/main.c

fix reason: Pin modification. Change SPI1 NSS PIN from PB12 to PB9。

V1.1.0:
void gpio_config(void)
{
    /* I2S0 GPIO config: I2S0_WS/PA4, I2S0_CK/PA5, I2S0_SD/PA7 */
    gpio_af_set(GPIOA, GPIO_AF_5, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7);
    
    /* I2S1 GPIO config: I2S1_WS/PB12, I2S1_CK/PB13, I2S1_SD/PB15 */
    gpio_af_set(GPIOB, GPIO_AF_5, GPIO_PIN_12|GPIO_PIN_13);        
    gpio_af_set(GPIOG, GPIO_AF_5, GPIO_PIN_3); 

    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ,GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7);

    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_15);
    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_12|GPIO_PIN_13 | GPIO_PIN_15);
}

V1.2.0:
void gpio_config(void)
{
    /* I2S0 GPIO config: I2S0_WS/PA4, I2S0_CK/PA5, I2S0_SD/PA7 */
    gpio_af_set(GPIOA, GPIO_AF_5, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7);
    
    /* I2S1 GPIO config: I2S1_WS/PB9, I2S1_CK/PB13, I2S1_SD/PB15 */
    gpio_af_set(GPIOB, GPIO_AF_5, GPIO_PIN_9|GPIO_PIN_13|GPIO_PIN_15);        

    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7);
    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ,GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7);

    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_9 | GPIO_PIN_13 | GPIO_PIN_15);
    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, GPIO_PIN_9|GPIO_PIN_13 | GPIO_PIN_15);
}
_________________________________________________________________________________________________________________________
______________________EXMC_________________________________________________________________________________________________
Fix file:
../Examples/EXMC/SDRAM/exmc_sdram.c

fix reason: Bug Fix.

V1.1.0:
void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
{
    ......
    /* step 8 : set the auto-refresh rate counter--------------------------------*/
    /* 64ms, 8192-cycle refresh, 64ms/8192=7.81us */
    /* SDCLK_Freq = SYS_Freq/2 */
    /* (7.81 us * SDCLK_Freq) - 20 */
    exmc_sdram_refresh_count_set(1151);
    ......
}

V1.2.0:
void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
{
    ......
    /* step 8 : set the auto-refresh rate counter--------------------------------*/
    /* 64ms, 8192-cycle refresh, 64ms/8192=7.81us */
    /* SDCLK_Freq = SYS_Freq/4 */
    /* (7.81 us * SDCLK_Freq) - 20 */
    exmc_sdram_refresh_count_set(566);
    ......
}
_________________________________________________________________________________________________________________________

******************* V1.1.0 2025-01-24 ******************************************************************************************
______________________Common_____________________________________________________________________________________________
Fix file:
../Firmware/CMSIS/GD/GD32H75E/Source/system_gd32h75e.c

fix reason: 
Delete function.

V1.0.0:
//#define SEL_PMU_SMPS_MODE   PMU_LDO_SUPPLY
//#define SEL_PMU_SMPS_MODE   PMU_DIRECT_SMPS_SUPPLY
//#define SEL_PMU_SMPS_MODE   PMU_SMPS_1V8_SUPPLIES_LDO
//#define SEL_PMU_SMPS_MODE   PMU_SMPS_2V5_SUPPLIES_LDO
//#define SEL_PMU_SMPS_MODE   PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO
//#define SEL_PMU_SMPS_MODE   PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO
//#define SEL_PMU_SMPS_MODE   PMU_SMPS_1V8_SUPPLIES_EXT
//#define SEL_PMU_SMPS_MODE   PMU_SMPS_2V5_SUPPLIES_EXT
//#define SEL_PMU_SMPS_MODE   PMU_BYPASS

V1.1.0:
//#define SEL_PMU_SMPS_MODE   PMU_LDO_SUPPLY
//#define SEL_PMU_SMPS_MODE   PMU_DIRECT_SMPS_SUPPLY
//#define SEL_PMU_SMPS_MODE   PMU_BYPASS
__________________________________________________________________________________________________________________________
______________________Common_____________________________________________________________________________________________
Fix file:
../Utilities/gd32h75ey_eval.c

fix reason: 
Modify the parameters of nvic_irq_enable/disable function. Remove type casting,  Resolve compilation warning issues.

V1.0.0:
static const IRQn_Type KEY_IRQn[KEYn]             = {WAKEUP_KEY_EXTI_IRQn, TAMPER_KEY_EXTI_IRQn, USER_KEY_EXTI_IRQn};

V1.1.0:
static const IRQn_Type KEY_IRQn[KEYn]           = {WAKEUP_KEY_EXTI_IRQn, TAMPER_KEY_EXTI_IRQn, USER_KEY_EXTI_IRQn};
__________________________________________________________________________________________________________________________
______________________CAN_____________________________________________________________________________________________
Fix file:
../Examples/CAN/Pretended_Networking_mode/main.c
../Examples/CAN/communication_FDmode/main.c
../Examples/CAN/communication_Loopback/main.c
../Examples/CAN/communication_classical_CAN/main.c

fix reason: 
Update the CAN_TX mode to AF+PULL UP to prevent CAN_TX from being accidentally pulled low.

V1.0.0:
gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_6);
gpio_mode_set(GPIOF, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7);
V1.1.0:
gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_6);
gpio_mode_set(GPIOF, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_7);
__________________________________________________________________________________________________________________________
______________________CAN_____________________________________________________________________________________________
Fix file:
../Examples/CAN/Pretended_Networking_mode/main.c
../Examples/CAN/communication_FDmode/main.c
../Examples/CAN/communication_classical_CAN/main.c

fix reason: 
 Modify the CAN clock source to RCU_CANSRC_APB2.

V1.0.0:
    rcu_can_clock_config(IDX_CAN0, RCU_CANSRC_APB2_DIV2);
    rcu_can_clock_config(IDX_CAN1, RCU_CANSRC_APB2_DIV2);
    rcu_can_clock_config(IDX_CAN2, RCU_CANSRC_APB2_DIV2)
V1.1.0:
    rcu_can_clock_config(IDX_CAN0, RCU_CANSRC_APB2);
    rcu_can_clock_config(IDX_CAN1, RCU_CANSRC_APB2);
    rcu_can_clock_config(IDX_CAN2, RCU_CANSRC_APB2);
__________________________________________________________________________________________________________________________
______________________CAN_____________________________________________________________________________________________
Fix file:
../Examples/CAN/communication_Loopback/main.c

fix reason: 
 Modify the CAN clock source to RCU_CANSRC_APB2.

V1.0.0:
    rcu_can_clock_config(IDX_CAN0, RCU_CANSRC_APB2_DIV2);
    rcu_can_clock_config(IDX_CAN1, RCU_CANSRC_APB2_DIV2);
    rcu_can_clock_config(IDX_CAN2, RCU_CANSRC_APB2_DIV2)
V1.1.0:
    rcu_can_clock_config(IDX_CAN0, RCU_CANSRC_APB2);
    rcu_can_clock_config(IDX_CAN1, RCU_CANSRC_APB2);
    rcu_can_clock_config(IDX_CAN2, RCU_CANSRC_APB2);
__________________________________________________________________________________________________________________________
______________________PMU_____________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_pmu.h

fix reason: 
Delete function.

V1.0.0:

V1.1.0:
Delete
#define PMU_CTL2_DVSCFG                 BIT(3)                              /*!< SMPS step-down converter forced on and in high power MR mode */
#define PMU_CTL2_DVSVC                  BITS(4,5)                           /*!< SMPS step-down converter voltage output level selection */
/* PMU step-down voltage stabilizer output level definitions */
#define CTL2_DVSVC(regval)              (BITS(4,5) & ((uint32_t)(regval) << 4U))
#define PMU_STEPDOWNVOL_1P8             CTL2_DVSVC(1)                       /*!< SMPS step-down converter voltage output level 1.8V */
#define PMU_STEPDOWNVOL_2P5             CTL2_DVSVC(2)                       /*!< SMPS step-down converter voltage output level 2.5V */

#define PMU_SMPS_1V8_SUPPLIES_LDO           (PMU_STEPDOWNVOL_1P8 | PMU_CTL2_DVSEN | PMU_CTL2_LDOEN)                     /*!< The SMPS 1.8V output supplies the LDO which supplies the V0.9V domains */
#define PMU_SMPS_2V5_SUPPLIES_LDO           (PMU_STEPDOWNVOL_2P5 | PMU_CTL2_DVSEN | PMU_CTL2_LDOEN)                     /*!< The SMPS 2.5V output supplies the LDO which supplies the V0.9V domains */
#define PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO   (PMU_STEPDOWNVOL_1P8 | PMU_CTL2_DVSCFG | PMU_CTL2_DVSEN | PMU_CTL2_LDOEN)   /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The V0.9V domains are suppplied from the LDO */
#define PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO   (PMU_STEPDOWNVOL_2P5 | PMU_CTL2_DVSCFG | PMU_CTL2_DVSEN | PMU_CTL2_LDOEN)   /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The V0.9V domains are suppplied from the LDO */
#define PMU_SMPS_1V8_SUPPLIES_EXT           (PMU_STEPDOWNVOL_1P8 | PMU_CTL2_DVSCFG | PMU_CTL2_DVSEN | PMU_CTL2_BYPASS)  /*!< The SMPS 1.8V output supplies an external source which supplies the V0.9V domains */
#define PMU_SMPS_2V5_SUPPLIES_EXT           (PMU_STEPDOWNVOL_2P5 | PMU_CTL2_DVSCFG | PMU_CTL2_DVSEN | PMU_CTL2_BYPASS)  /*!< The SMPS 2.5V output supplies an external source which supplies the V0.9V domains */
__________________________________________________________________________________________________________________________
______________________PMU_____________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Include/gd32h75e_pmu.h

fix reason: 
Delete function.

V1.0.0:
/* check PMU power supply */
#define NOT_PMU_SMPS_LDO_SUPPLY(smpsmode)                (((smpsmode) != PMU_LDO_SUPPLY) && ((smpsmode) != PMU_DIRECT_SMPS_SUPPLY) && \
                                                         ((smpsmode) != PMU_SMPS_1V8_SUPPLIES_LDO) && ((smpsmode) != PMU_SMPS_2V5_SUPPLIES_LDO) && \
                                                         ((smpsmode) != PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && ((smpsmode) != PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && \
                                                         ((smpsmode) != PMU_SMPS_1V8_SUPPLIES_EXT) && ((smpsmode) != PMU_SMPS_2V5_SUPPLIES_EXT) && \
														 ((smpsmode) != PMU_BYPASS))
V1.1.0:
/* check PMU power supply */
#define NOT_PMU_SMPS_LDO_SUPPLY(smpsmode)                (((smpsmode) != PMU_LDO_SUPPLY) && ((smpsmode) != PMU_DIRECT_SMPS_SUPPLY) && \
														 ((smpsmode) != PMU_BYPASS))
__________________________________________________________________________________________________________________________
______________________PMU_____________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_standard_peripheral/Source/gd32h75e_pmu.c

fix reason: 
Delete function.

V1.0.0:
/*!
    \brief      power supply configurations
    \param[in]  smpsmode:
                only one parameter can be selected which is shown as below:
      \arg        PMU_LDO_SUPPLY: V0.9V domains are suppplied from the LDO
      \arg        PMU_DIRECT_SMPS_SUPPLY: V0.9V domains are suppplied from the SMPS only
      \arg        PMU_SMPS_1V8_SUPPLIES_LDO: the SMPS 1.8V output supplies the LDO which supplies the V0.9V domains
      \arg        PMU_SMPS_2V5_SUPPLIES_LDO: the SMPS 2.5V output supplies the LDO which supplies the V0.9V domains
      \arg        PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO: the SMPS 1.8V output supplies an external circuits and the LDO. The V0.9V domains are suppplied from the LDO
      \arg        PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO: the SMPS 2.5V output supplies an external circuits and the LDO. The V0.9V domains are suppplied from the LDO
      \arg        PMU_SMPS_1V8_SUPPLIES_EXT: the SMPS 1.8V output supplies an external source which supplies the V0.9V domains
      \arg        PMU_SMPS_2V5_SUPPLIES_EXT: the SMPS 2.5V output supplies an external source which supplies the V0.9V domains
      \arg        PMU_BYPASS: the SMPS disabled and the LDO Bypass. The V0.9V domains are supplied from an external source
    \param[out] none
    \retval     none
*/
void pmu_smps_ldo_supply_config(uint32_t smpsmode)
{
#ifdef FW_DEBUG_ERR_REPORT
    if(NOT_PMU_SMPS_LDO_SUPPLY(smpsmode)) {
        fw_debug_report_err(PMU_MODULE_ID, API_ID(0x0015U), ERR_PARAM_INVALID);
    } else
#endif /* FW_DEBUG_ERR_REPORT */
    {
        uint32_t temp;
        temp = PMU_CTL2;
        temp &= ~(PMU_CTL2_DVSVC | PMU_CTL2_DVSCFG | PMU_CTL2_DVSEN | PMU_CTL2_LDOEN | PMU_CTL2_BYPASS);
        temp |= smpsmode;
        PMU_CTL2 = temp;

        while(0U == (PMU_CTL3 & PMU_CTL3_VOVRF)) {
        }

        /* When the SMPS supplies external circuits verify that DVSRF flag is set */
        if((smpsmode == PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
                (smpsmode == PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO)   ||
                (smpsmode == PMU_SMPS_1V8_SUPPLIES_EXT)           ||
                (smpsmode == PMU_SMPS_2V5_SUPPLIES_EXT)) {
            while(0U == (PMU_CTL2 & PMU_CTL2_DVSRF)) {
            }
        }
    }
}

V1.1.0:
/*!
    \brief      power supply configurations
    \param[in]  smpsmode:
                only one parameter can be selected which is shown as below:
      \arg        PMU_LDO_SUPPLY: V0.9V domains are suppplied from the LDO
      \arg        PMU_DIRECT_SMPS_SUPPLY: V0.9V domains are suppplied from the SMPS only
      \arg        PMU_BYPASS: the SMPS disabled and the LDO Bypass. The V0.9V domains are supplied from an external source
    \param[out] none
    \retval     none
*/
void pmu_smps_ldo_supply_config(uint32_t smpsmode)
{
#ifdef FW_DEBUG_ERR_REPORT
    if(NOT_PMU_SMPS_LDO_SUPPLY(smpsmode)) {
        fw_debug_report_err(PMU_MODULE_ID, API_ID(0x0015U), ERR_PARAM_INVALID);
    } else
#endif /* FW_DEBUG_ERR_REPORT */
    {
        uint32_t temp;
        temp = PMU_CTL2;
        temp &= ~(PMU_CTL2_DVSEN | PMU_CTL2_LDOEN | PMU_CTL2_BYPASS);
        temp |= smpsmode;
        PMU_CTL2 = temp;

        while(0U == (PMU_CTL3 & PMU_CTL3_VOVRF)) {
        }
    }
}
________________________________________________________________________________________________________________________
______________________USB_____________________________________________________________________________________________
Fix file:
../Firmware/GD32H75E_usbhs_library/host/core/Source/usbh_core.c

fix reason: 
Bug fix.

V1.0.0:
        uhost->active_class->class_deinit(uhost);
        break;

    case HOST_DEV_DETACHED:
        /* manage user disconnect operations*/
        uhost->usr_cb->dev_detach();

        /* re-initialize host for new enumeration */
        usbh_deinit(uhost);
        uhost->usr_cb->dev_deinit();
        uhost->active_class->class_deinit(uhost);
V1.1.0:
        if (uhost->active_class != NULL) {
        uhost->active_class->class_deinit(uhost);
        };
        break;

    case HOST_DEV_DETACHED:
        /* manage user disconnect operations*/
        uhost->usr_cb->dev_detach();

        /* re-initialize host for new enumeration */
        usbh_deinit(uhost);
        uhost->usr_cb->dev_deinit();
        if (uhost->active_class != NULL) {
        uhost->active_class->class_deinit(uhost);
        };
__________________________________________________________________________________________________________________________